Codes have been used to detect and/or correct errors in data that has been stored in memory or transmitted from one location to another. A simple error detection code is based on parity. A parity bit is added to a group of data bits, such as a data word, and has a logic state that is selected to make the total number of “1s” (or “0s”) in the data word either even or odd. The original data word is then transmitted or stored along with the additional parity bit as a modified data word. In a memory storage system, when the modified data word is read from memory a detection circuit checks the parity of the modified data word against an expected value. If the parity is correct, the detection circuit assumes there are no bit errors. If the parity is incorrect, the detection circuit assumes there is an error in the retrieved data.
More complex error correction codes (ECCs) have also been used for enabling not only detection of errors but also correction of the detected errors. For example, a single-error correction, double-error detection (SEC-DED) Hamming code adds enough additional parity bits to enable the detection circuit to detect and correct any single-bit error in a data word and detect double-bit errors. Other types of error correction codes include convolution (tree) codes and other block codes. In these types of ECC codes, one or more data words are divided into blocks of data and each block of data is encoded into a longer block of data. With convolution codes, the encoding of one block of data depends on the state of the encoder as well as the data to be encoded. With block codes, each block of data is encoded independently from every other block of data.
Recently, there has been an increased interest in using ECC codes while writing data to and reading data from integrated circuit memories, such as random access memories (RAMs), dynamic random access memories (DRAMs), and double data rate (DDR) DRAMs. These memories can be embedded on the integrated circuit containing the data source or can be external to the integrated circuit. The use of ECC codes with integrated circuit memories has been found to reduce problems with random cell errors in memory arrays.
However, the introduction of error code generation circuitry within the write data path, between the data source and the memory, can negatively affect the performance of the memory since the new circuitry adds delay to this critical timing path. This is particularly true with certain data sources, such as processors that require access to the memory within a single clock cycle. One example of such a configuration is a processor having a “tightly-coupled memory.”
Due to continually shrinking technology feature sizes and the inherent lower voltage thresholds (VH, VL), configurations as those mentioned above, namely the “tightly-coupled memory”, are more susceptible to the effects of cosmic radiation. The cosmic radiation (charged particles), and the effect on the voltage thresholds is the cause for the increase in memory soft error rates.
Another difficulty with implementing error detection and/or correction codes occurs when the memory interface must support byte-based memory accesses while implementing word-based ECC codes. A word-based ECC code is more desirable than a byte-based ECC code since a word-based ECC code requires less code bits. For example, a byte-based ECC code may require 52 bits for a 32-bit data word while a word-based ECC code may require only 39 bits. The data words can have any number of bits.
Byte write accesses with word-based ECC codes are accomplished through “read/modify/write” operations. A read/modify/write operation is performed when the data source attempts to write a smaller number of bits (such as a byte) than the width of the ECC block (such as a data word). An ECC block is defined as the basic unit of data from which the ECC bits apply. When partial ECC block writes are executed, the memory interface must read the original data that is stored in the targeted memory location and then merge that read data with the new data, byte or half-word, to form a full ECC block. The appropriate ECC bits are then generated for the full ECC block and the data is written to memory. This read/modify/write operation can take a number of extra clock cycles to complete due to wait state and/or higher priority read operations, for example.
Improved memory interfaces are therefore desired, which do not significantly impact the critical timing paths to the memory and which allow partial writes without significantly impacting the latency seen by the data source.